1. Field of the Invention
The present invention relates to a semiconductor device layout structure, and in particular to a vertical diffusion super junction device layout structure.
2. Description of the Related Art
The conventional vertical diffusion metal-oxide-semiconductor field effect transistor (VDMOSFET) has a p-n junction structure composed of an n-type drift doped region and an overlying p-type base doped region. The p-n junction structure is mainly used to withstand a voltage applied to the conventional VDMOSFET. When improving an operation voltage of the VDMOSFET, a reduced dopant concentration and an increased thickness of the n-type drift doped region is required. The ways to improve a withstand voltage of the p-n junction structure results in an increased on-resistance (Ron) for the conventional VDMOSFET. Ron of the conventional VDMOSFET is limited by the dopant concentration and the thickness of the n-type drift doped region. A VDMOSFET having a super junction structure has been developed to improve the dopant concentration of the n-type drift doped region, so that Ron of the VDMOSFET can be improved.
The conventional super junction structure is usually fabricated by a multi-epitaxy technology (COOLMOS™). The multi-epitaxy technology requires performing several process cycles of an epitaxy growing process, a p-type dopant implantation process and a thermal diffusion process. Therefore, the multi-epitaxy technology has the drawbacks of having plenty of processing steps, and a high fabrication cost. Also, the dimensions of the VDMOSFET are hard to reduce.
Thus, a semiconductor device layout structure having a super junction structure is desired.